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| NCN6000 Compact Smart Card Interface IC The NCN6000 is an integrated circuit dedicated to the smart card interface applications. The device handles any type of smart card through a simple and flexible microcontroller interface. On top of that, due to the built-in chip select pin, several couplers can be connected in parallel. The device is particularly suited for low cost, low power applications, with high extended battery life coming from extremely low quiescent current. Features http://onsemi.com MARKING DIAGRAM 20 1 TSSOP-20 DTB SUFFIX CASE 948E 1 A = Assembly Location L = Wafer Lot Y = Year W = Work Week G = Pb-Free Package (Note: Microdot may be in either location) NCN 6000 ALYWG G * 100% Compatible with ISO7816-3 and EMV Standard * Wide Battery Supply Voltage Range: 2.7 v Vbat v 6.0 V * Programmable CRD_VCC Supply to Cope with either 3.0 V or 5.0 V Card Operation * Built-in DC-DC Converter Generates the CRD_VCC Supply with a * * * * * * * * Single External Low Cost Inductor only, providing a High Efficiency Power Conversion Full Control of the Power Up/Down Sequence Yields High Signal Integrity on both the Card I/O and the Signal Lines Programmable Card Clock Generator Built-in Chip Select Logic allows Parallel Coupling Operation ESD Protection on Card Pins (8.0 kV, Human Body Model) Fault Monitoring includes Vbatlow and Vcclow, providing Logic Feedback to External CPU Card Detection Programmable to Handle Positive or Negative Going Input Built-in Programmable CRD_CLK Stop Function Handles both High or Low State These are Pb-Free Devices** PIN CONNECTIONS A0 1 A1 2 PGM 3 PWR_ON 4 STATUS 5 CS 6 RESET 7 I/O 8 INT 9 CLOCK_IN 10 (Top View) 20 Vbat 19 Lout_H 18 Lout_L 17 PWR_GND 16 GROUND 15 CRD_VCC 14 CRD_IO 13 CRD_CLK 12 CRD_RST 11 CRD_DET Typical Application * E-Commerce Interface * ATM Smart Card * Pay TV System ORDERING INFORMATION Device NCN6000DTB ISO/EMV NCN6000DTBG NCN6000DTBR2 NCN6000 SMART CARD INTERFACE Package TSSOP-20* TSSOP-20* Shipping 75 Units / Rail 75 Units / Rail MICRO CONTROLLER TSSOP-20* 2500/Tape & Reel NCN6000DTBR2G TSSOP-20* 2500/Tape & Reel For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D. *This package is inherently Pb-Free. Figure 1. Simplified Application **For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D. (c) Semiconductor Components Industries, LLC, 2006 1 March, 2006 - Rev. 4 Publication Order Number: NCN6000/D NCN6000 +5 V VCC 1 PB7 PB6 3 PB5 PB4 PB3 PB2 PB1 PB0 IRQ 10 XTAL MCU GND 4 5 6 7 8 9 2 A0 A1 PGM U1 Vbat Lout_H Lout_L C1 20 19 18 17 16 15 14 13 12 11 GND 17 18 8 4 3 2 GND GND 1 5 7 Swa Swb C8 C4 CLK RST VCC GND I/O VPP ISO7816 GND C2 C3 10 mF 100 nF GND GND L1 22 mH 10 mF GND PWR_ON PWR_GND STATUS CS RESET I/O INT GROUND CRD_VCC CRD_IO CRD_CLK CRD_RST CLOCK_IN CRD_DET NCN6000 J1 SMARTCARD Figure 2. Typical Application http://onsemi.com 2 NCN6000 +Vbat Vbat_OK 50 k INT 9 50 ms Delay CARD DETECTION POLARITY PROGRAMMABLE STATUS INT 500 k Q GND S R GND 11 CRD_DET + - 2.0 V Vbat 20 Vbat +Vbat 50 k CS 6 CLK STOP PGM A1 A0 3 2 1 1/1 1/2 1/4 1/8 STATUS INT DC-DC STATUS ENABLE VCC Vbat VCC DECODER 1:16 Fout DATA SELECT Set_VCC CLOCK DC-DC CONVERTER 3V/5V Power Down Active Pwr_Down GND FAULT ON/OFF VCC 15 CRD_VCC 19 Lout_H 18 Lout_L 17 PWR_GND CLOCK_IN 10 CLOCK DIVIDER 16 GROUND GND CARD STATUS PWR_ON 4 Vbat SEQ 1 SEQ 2 50 k STATUS 5 2 A GND Vbat_OK I/O 8 1 Vbat LOGIC & CARD PINS SEQUENCER SEQ 3 Vbat_OK CLOCK CLK_STOP SEQ 2 CLOCK 13 CRD_CLK 20 k 20 k SEQ 1 DATA I/O Vbat 3 I/O DATA 14 CRD_IO 1 RESET 7 2 SEQ 3 PWR_ON RESET 12 CRD_RST Figure 3. Block Diagram http://onsemi.com 3 STATUS Program Chip PGM RESET A1 A0 I/O CS A0 I/O L H L H L H L H L H L H Reserved CRD_DET = Normally Open CRD_DET = Normally Close CRD_DET = Normally Close CRD_DET = Normally Close Read STATUS = 1-> Card Present/ = 0-> No Card Read STATUS = 1->DC-DCOK/ = 0-> DC-DC Overloaded Read Vbat status-> Low = Battery OK Read CRD_VCC status-> Low = CRD_VCC Low Voltage L H L H Z Z Z Z STOP CRD_CLKLow STOP CRD_CLKHigh 5 V CLOCK_IN 1/8 ENABLE CRD_CLK 5 V CLOCK_IN 1/2 5 V CLOCK_IN 1/4 3 V CLOCK_IN 1/8 5 V CLOCK_IN 1/1 3 V CLOCK_IN 1/2 3 V CLOCK_IN 1/4 3 V CLOCK_IN 1/1 L L H H L L H H L L H H L L H H L H L H Normal Chip Operation CARD PRESENT NO CARD DC-DC OK DC-DC OVERLOADED STATUS PGM RESET A1 1 - L L L 2 - L L L 3 - L L L 4 - L L L 5 - L L H 6 - L L H NCN6000 http://onsemi.com Figure 4. Programming and Normal Operation Basic Timing 4 7 - L L H 8 - L L H 9 - - L L H H L L 10 11 - L H L 12 - L H L 13 - L H H 14 - L H H 15 - L H H 16 - L H H 17 H/L H Z L 18 H/L H Z L 19 L/H H Z H 20 H/L H Z H NCN6000 The programming can be achieved with the card powered ON or OFF. The identification of the interrupt is carried out by polling the STATUS pin, the Vbat voltage and the DC-DC results being provided on the same pin as depicted by the table in Figure 4. During the programming mode, the PGM pin can be released to High since the mode is internally latched by the Negative going transition presents on the Chip Select pin. INTERRUPT ACKNOWLEDGE 50 ms CRD_DET INT CS PGM CARD IDENTIFICATION POLLING CARD EXTRACTED 50 ms High A0 A1 STATUS Low Low S1 CLEAR INTERRUPT S2 CARD PRESENT: STATUS = 1 S3 CLEAR INTERRUPT S4 CARD PRESENT: STATUS = 0 Figure 5. Interrupt Servicing and Card Polling When a card is either inserted or extracted, the CRD_DET pin signal is debounced internally prior to pull the INT pin to Low. The built-in logic circuit automatically accommodates positive or negative input signal slope, on both insertion and extraction state, depending upon the polarity defined during the initialization sequence. The default condition is Normally Open switch, negative going card detection. The external CPU shall acknowledge the request by forcing CS = L which, in turn, releases the INT pin to High upon positive going of Chip Select (Table 4). Polling the STATUS pin as depicted in Table 3 identifies the active card. If a card is present, the STATUS returns High, otherwise a Low is presented pin 5. The 50 ms digital filter is activated during both Insertion and Extraction of the card. The MPU shall clear the INT line when the card has been extracted, making the interrupt function available for other purposes. However, neither the NCN6000 operation nor the smart card I/O line or commands are affected by the state of the INT pin. On the other hand, clearing the INT and reading the STATUS register can be performed by a single read by the MPU: states S1 and S2 can be combined in a single instruction, the same for S3 and S4. http://onsemi.com 5 NCN6000 ABBREVIATIONS Lout_H Lout_L Cout VCC Icc Class A Class B CS Z CRD_VCC CRD_CLK CRD_RST CRD_IO CRD_DET ATR PGM INT tr tf td ts DC-DC External Inductor DC-DC External Inductor Output Capacitor Card Power Supply Input Current at CRD_VCC Pin 5.0 V Smart Card 3.0 V Smart Card Chip Select (from MPU) High Impedance Logic State (according to ISO7816) Interface IC Card Power Supply Output Interface IC Card Clock Output Interface IC Card Reset Output Interface IC Card I/O Signal Line Interface IC Card Detection Answer to Reset Select Programming or Normal Operation Interrupt (to MPU) Rise Time Fall Time Delay Time Storage Time PIN FUNCTIONS AND DESCRIPTION Pin 1 2 3 4 Name A0 A1 PGM PWR_ON Type INPUT INPUT INPUT INPUT Pull Down Description This pin is combined with A1, PGM, RESET and I/O to program the chip mode of operation and to read the data provided by STATUS. (Figures 4 and 5 and Tables 2 and 3) This pin is combined with A0, PGM, RESET and I/O to program the chip mode of operation and to read the data provided by STATUS. (Figures 4 and 5 and Tables 2 and 3) This pin is combined with A0, A1, RESET and I/O to program the chip mode of operation and to read the data provided by STATUS. (Figures 4 and 5 and Tables 2 and 3) This pin validates the operation of the internal DC-DC converter: CS = L + PWR_ON = Negative going: DC-DC is OFF CS = L + PWR_ON = Positive going: DC-DC is ON Note: The PWR_ON bit must be combined with a Low state CS signal to activate the function. (Table 2) This pin provides logic state related to the card and NCN6000 status. According to the A0, A1 and PGM logic state, this pin carries either the Card present status or the Vbat or the DC-DC operation state. When PGM = L, STATUS is not affected, see Table 2. This pin provides the NCN6000 chip select function. The PWR_ON, RESET, I/O, A0, A1 and PGM signals are disabled when CS = H. When PGM = L and CS = L, the device jumps to the programming mode (Figure 4 and Tables 1, 2 and 3). The Chip Select pin must be a unique physical address when more than one card are controlled by a single MPU. The data presented by the MPU are latched upon positive going edge of the Chip Select pin. This pin provides two modes of operation depending upon the logic state of PGM pin 3: PGM = 1: The signal present at this pin is translated to pin 12 (card reset signal) when CS = L and PWR_ON = H. It is latched when CS = H. PGM = 0: The signal present on this pin is used as a logic input to program the internal functions (Figure 5 and Tables 2 and 3). 5 STATUS OUTPUT 6 CS INPUT Pull Up 7 RESET INPUT Pull Down http://onsemi.com 6 NCN6000 PIN FUNCTIONS AND DESCRIPTION (continued) Pin 8 Name I/O Type Input/Output Pull Up Description This pin is connected to an external microcontroller interface. A bidirectional level translator adapts the serial I/O signal between the smart card and the microcontroller. The level translator is enabled when CS = L. The signal present on this pin is latched when CS = H. This pin is also used in programming mode (Tables 1, 2 and 3, Figures 4 and 5). This pin is activated LOW when a card has been inserted and detected by the interface or when the NCN6000 reports Vbat or CRD_VCC status (See Table 6). The signal is reset to a logic 1 on the rising edge of either CS or PWR_ON. The Collector open mode makes possible the wired AND/OR external logic. When two or more interfaces share the INT function with a single microcontroller, the software must poll the STATUS pin to identify the origin of the interrupt (Figure 5). This pin can be connected to either the microcontroller master clock, or to any clock signal, to drive the external smart cards. The signal is fed to internal clock selector circuit and translated to the CRD_CLK pin at either the same frequency, or divided by 2 or 4 or 8, depending upon the programming mode (Tables 1, 2 and 3). Care must be observed, at PCB level, to minimize the pick-up noise coming from the CLOCK_IN line. It is recommended to put a shield, built with a 10 mil copper track, around this line and terminated to the GND. The signal coming from the external card connector is used to detect the presence of the card. A built-in pull up low current source makes this pin active LOW or HIGH, assuming one side of the external switch is connected to ground. At Vbat start up, the default condition is Normally Open switch, negative going insertion detection. The Normally Closed switch, positive going insertion detection, can be defined by programming the NCN6000 accordingly. In this case, the polarity must be set up during the first cycles of the system initialization, otherwise an already inserted card will not be detected by the chip. This pin is connected to the RESET pin of the card connector. A level translator adapts the RESET signal from the microcontroller to the external card. The output current is internally limited to 15 mA. The CRD_RST is validated when PWR_ON = H and PGM = H and hard wired to Ground when the card is deactivated. This pin is connected to the CLK pin of the card connector. The CRD_CLK signal comes from the clock selector circuit output. Combining A0, A1, PGM and I/O, as depicted in Table 3 and Figure 3, programs the clock selection. This signal can be forced into a standby mode with CRD_CLK either High or Low, depending upon the mode defined by the programming sequence (Tables 1, 2 and 3 and Figure 4). Care must be observed, at PCB level, to minimize the pick-up noise coming from the CRD_CLK line. It is recommended to put a shield, built with a 10mil copper track, around this line and terminated to the GND. This pin handles the connection to the serial I/O pin of the card connector. A bidirectional level translator adapts the serial I/O signal between the card and the microcontroller. The CRD_IO pin current is internally limited to 15 mA. A built-in register holds the previous state presents on the I/O input pin. This pin provides the power to the external card. It is the logic level "1" for CRD_IO, CRD_RST and CRD_CLK signals. The energy stored by the DC-DC external inductor Lout must be smoothed by a 10 mF capacitor, associated with a 100 nF ceramic in parallel, connected across CRD_VCC and GND. In the event of a CRD_VCC UVLOW voltage, the NCN6000 detects the situation and feedback the information in the STATUS bit. The device does not take any further action, particularly the DC-DC converter is neither stopped nor reprogrammed by the NCN6000. It is up to the external MPU to handle the situation. However, when the CRD_VCC is overloaded, the NCN6000 shut off the DC-DC converter, pulls the INT pin Low and reports the fault in the STATUS register. The logic and low level analog signals shall be connected to this ground pin. This pin must be externally connected to the PWR_GND pin 17. The designer must make sure no high current transients are shared with the low signal currents flowing into this pin. This pin is the Power Ground associated with the built-in DC-DC converter and must be connected to the system ground together with GROUND pin 11. Using good quality ground plane is recommended to avoid spikes on the logic signal lines. The High Side of the external inductor is connected between this pin and Lout_H to provide the DC-DC function. The built-in MOS devices provide the switching function together with the CRD_VCC voltage rectification. 9 INT OUTPUT Pull Down 10 CLOCK_IN CLOCK INPUT High Impedance 11 CRD_DET INPUT 12 CRD_RST OUTPUT 13 CRD_CLK OUTPUT 14 CRD_IO I/O 15 CRD_VCC POWER 16 GROUND SIGNAL 17 PWR_GND POWER 18 Lout_L POWER http://onsemi.com 7 NCN6000 PIN FUNCTIONS AND DESCRIPTION (continued) Pin 19 Name Lout_H Type POWER Description The High Side of the external inductor is connected between this pin and Lout_L to provide the DC-DC function. The current flowing into this inductor is limited by a sense resistor internally connected from Vbat/pin 20 and pin 19. Typically, Lout = 22 mH, with ESR < 2.0 W, for a nominal 55 mA output load. This pin is connected to the supply voltage and monitored by the NCN6000. The operation is inhibited when Vbat is below the minimum 2.70 V value, followed by a PWR_DOWN sequence and a Low STATUS state. 20 Vbat POWER MAXIMUM RATINGS (Note 1) Rating Battery Supply Voltage Battery Supply Current (Note 2) Power Supply Voltage Power Supply Current Digital Input Pins Digital Input Pins Digital Output Pins Digital Output Pins Card Interface Pins Card Interface Pins, except CRD_CLK Inductor Current ESD Capability (Note 3) Standard Pins Card Interface Pins and CRD_DET TSSOP-20 Package Power Dissipation @ Tamb = +85C Thermal Resistance Junction to Air (Rqja) Operating Ambient Temperature Range Operating Junction Temperature Range Maximum Junction Temperature (Note 4) Storage Temperature Range Symbol Vbat Ibat Vcc Icc Vin Iin Vout Iout Vcard Icard ILout VESD 2.0 8.0 PDS Rqja TA TJ TJmax Tsg 320 125 -25 to +85 -25 to +125 +150 -65 to +150 mW C/W C C C C Value 7.0 300 6.0 "100 -0.5 V < Vin < Vbat +0.5 V, but < 7.0 V "5.0 -0.5 V < Vin < Vbat +0.5 V, but < 7.0 V "10 -0.5 V < Vcard < CRD_VCC +0.5 V "15 300 Unit V mA V mA V mA V mA V mA mA kV Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability. 1. Maximum electrical ratings are defined as those values beyond which damage to the device may occur at TA = +25C. 2. This current represents the maximum peak current the pin can sustain, not the NCN6000 consumption (see Ibatop). 3. Human Body Model, R = 1500 W, C = 100 pF. 4. Absolute Maximum Rating beyond which damage to the device may occur. http://onsemi.com 8 NCN6000 POWER SUPPLY SECTION (-25C to +85C ambient temperature, unless otherwise noted.) Rating Power Supply Standby Supply Current Conditions: PWR_ON = L, STATUS = H, CLOCK_IN = H, CS = H. All other logic inputs and outputs are open: Vbat = 3.0 V Vbat = 5.0 V DC Operating Current (Figure 19) PWR_ON = H, CLOCK_IN = 0, CS = H, all CRD pins unloaded @ Vbat = 6.0 V, CRD_VCC = 5.0 V @ Vbat = 3.6 V, CRD_VCC = 5.0 V Vbat Undervoltage DetectionHigh Vbat Undervoltage DetectionLow Vbat Undervoltage DetectionHysteresis Output Card Supply Voltage @ Icc = 55 mA @ 2.70 V vVbat v6.0 V CRD_VCC = 3.0 V CRD_VCC = 5.0 V @ VbatLL < Vbat < 2.70 V CRD_VCC = 5.0 V Output Card Supply Peak Current @ Vcc = 5.0 V @ CRD_VCC = 5.0 V @ CRD_VCC = 3.0 V @ Vbat = 3.6 V, CRD_VCC = 5.0 V, Tamb < 65C Output Current Limit Time Out Output Over Current Limit Output Dynamic Peak Current @ CRD_VCC = 3.0 V or 5.0 V, Cout = 10 mF Ceramic XR7, Pulse Width 400 ns (Notes 5 and 6) Battery Start-Up Current @ CRD_VCC = 3.0 V, -25C v TA v+ 85C @ CRD_VCC = 5.0 V, -25CvTAv+ 85C Output Card Supply Voltage Ripple @ Lout = 22 mH, Cout 1 = 10 mF, Cout 2 = 100 nF, Vbat = 3.6 V Iout = 55 mA CRD_VCC = 5.0 V (Note 5) CRD_VCC = 3.0V Output Card Supply Turn On Time @ Lout = 22 mF, Cout1 = 10 mF, Cout2 = 100 nF, Vbat = 2.7 V, CRD_VCC = 5.0 V Output Card Supply Shut Off Time @ Cout1 = 10 mF, Ceramic, Vbat = 2.7 V, CRD_VCC = 5.0 V, VccOFF < 0.4 V DC-DC Converter Operating Frequency Power Switch Drain/Source Resistor Output Rectifier ON Resistor Symbol Vbat Ibatsb Pin 20 20 Min 2.7 Typ - Max 6.0 Unit V mA - - Ibatop 20 3.0 - 8.0 15 mA - - VbatLH VbatLL VbatHY Vcc VC3H VC5H VC5H Iccp 15 55 55 65 tdoff Iccov Iccd 15 15 15 - - 100 20 2.1 2.0 - 7.0 2.0 - - 100 - 5.0 2.7 2.6 - V V mV V 15 2.75 4.75 4.50 - - - - - - 4.0 - - 3.25 5.25 - mA - - - - 100 - ms mA mA Iccst 20 - - 140 300 - - mA Vccrip 15 - - - - - 50 50 2.0 mV VccTON 15 - ms VccTOFF 15 - - 250 ms Fsw RONS ROND 18 18 15 - - - 600 1.9 2.8 - 2.2 3.4 kHz W W 5. Ceramic X7R, SMD types capacitors are mandatory to achieve the CRD_VCC specifications. When electrolytic capacitor is used, the external filter must include a 100 nF, max 50 mW ESR capacitor in parallel, to reduce both the high frequency noise and ripple to a minimum. Depending upon the PCB layout, it might be necessary is to use two 6.8 mF/10 V/ceramic/X7R//SMD1206 in parallel, yielding an improved CRD_VCC ripple over the temperature range. 6. According to ISO7816-3, paragraph 4.3.2. http://onsemi.com 9 NCN6000 DIGITAL PARAMETERS SECTION @ 2.70 VvVbatv6.0 V, NORMAL OPERATING MODE (-25C to +85C ambient temperature, unless otherwise noted.) Note: Digital inputs undershoot < -0.30 V to ground, Digital inputs overshoot <0.30 V to Vbat Rating Input Asynchronous Clock Duty Cycle = 50% @ Vbat = 3.0V over the temperature range Clock Rise Time Clock Fall Time I/O Data Transfer Switching Time, Both Directions (I/O and CRD_IO), @ Cout = 30 pF I/O Rise Time* (Note 7) I/O Fall Time Input/Output Data Transfer Time, Both Directions @ 50% CRD_VCC, L to H and H to L Minimum PWR_ON Low Level Logic State Time to Power Down the DC-DC Converter CRD_VCC Power Up/Down Sequence Interval STATUS Pull Up Resistance Chip Select CS Pull Up Resistance Interrupt INT Pull Up Resistance Positive Going Input High Voltage Threshold (A0, A1, PGM, PWR_ON, CS, RESET, CRD_DET) Symbol FCLKIN Ftr Ftf Pin 10 10 8, 14 Min - - - - Typ - 40 - - - 5.0 5.0 MHz ns ms Max Unit TRIO TFIO TTIO TWON TDSEQ RSTA RCSPU RINTPU VIH 5 6 9 1, 2, 3, 4, 6, 7, 11 1, 2, 3, 4, 6, 7, 11 5, 9 5, 9 8, 14 4 - 2.0 - 20 20 20 0.70 * Vbat - - 0.5 50 50 50 - 0.8 0.8 150 - 2.0 80 80 80 Vbat ns ms ms kW kW kW V Negative Going Input High Voltage Threshold (A0, A1, PGM, PWR_ON, CS, RESET, CRD_DET) Output High Voltage STATUS, INT @ IOH = -10 mA Output High Voltage STATUS, INT @ IOH = 200 mA VIL 0 - 0.30 * Vbat V VOH VOL Vbat - 1.0 V - - - - 0.40 V V 7. Since a 20 kW pull up resistor is provided by the NCN6000, the external MPU can use an Open Drain connection. DIGITAL PARAMETERS SECTION @ 2.70 VvVbatv6.0 V, CHIP PROGRAMMING MODE (-25C to +85C ambient temperature, unless otherwise noted.) Rating A0, A1, PGM, PWR_ON, RESET and I/O Data Set Up Time A0, A1, PGM, PWR_ON, RESET and I/O Data Set Up Time Chip Select CS Low State Pulse Width Symbol TSMOD Pin 1, 2, 3, 4, 7, 8 1, 2, 3, 4, 7, 8 6 Min 2.0 Typ - Max - ms 2.0 - - ms 2.0 - - ms Unit THMOD TWCS http://onsemi.com 10 NCN6000 SMART CARD SECTION (-25C to +85C ambient temperature, unless otherwise noted.) Rating CRD_RST @ CRD_VCC = +5.0 V Output RESET VOH @ Icrd_rst = -20 mA Output RESET VOL @ Icrd_rst = 200 mA Output RESET Rise Time @ Cout = 30 pF Output RESET Fall Time @ Cout = 30 pF CRD_RST @ Vcc = +3.0 V Output RESET VOH @ Icrd_rst = -20 mA Output RESET VOL @ Icrd_rst = 200 mA Output RESET Rise Time @ Cout = 30 pF Output RESET Fall Time @ Cout = 30 pF CRD_CLK @ CRD_VCC = +3.0 V or +5.0 V CRD_VCC = +5.0 V Output Frequency (See Note 8) Output Duty Cycle @ DC Fin = 50% "1% Output CRD_CLK Rise Time @ Cout = 30 pF Output CRD_CLK Fall Time @ Cout = 30 pF Output VOH @ Icrd_clk = -20 mA Output VOL @ Icrd_clk = 100 mA CRD_VCC = +3.0 V Output Frequency (See Note 8) Output Duty Cycle @ DC Fin = 50% "1% Output CRD_CLK Rise Time @ Cout = 30 pF Output CRD_CLK Fall Time @ Cout = 30 pF Output VOH @ Icrd_clk = -20 mA @ Cout = 30 pF Output VOL @ Icrd_clk = 100 mA @ Cout = 30 pF CRD_I/O @ CRD_VCC = +5.0 V CRD_I/O Data Transfer Frequency CRD_I/O Rise Time @ Cout = 30 pF CRD_I/O Fall Time @ Cout = 30 pF Output VOH @ Icrd_i/o = -20 mA Output VOL @ Icrd_i/o = 500 mA, VIL = 0 V CRD_I/O @ CRD_VCC = +3.0 V CRD_I/O Data Transfer Frequency CRD_I/O Rise Time @ Cout = 30 pF CRD_I/O Fall Time @ Cout = 30 pF Output VOH @ Icrd_i/o = -20 mA Output VOL @ Icrd_i/o = 500 mA, VIL = 0 V CRD_IO Pull Up Resistor @ PWR_ON = H Card Detection Debouncing Delay: Card Insertion Card Extraction Card Insertion or Extraction Positive Going Input High Voltage Card Insertion or Extraction Negative Going Input Low Voltage Card Detection Bias Pull Up Current @ Vbat = 5.0 V Output Peak Max Current Under Card Static Operation Mode @ Vcc = 3.0 V or Vcc = 5.0 V Output Peak Max Current Under Card Static Operation Mode @ Vcc = 3.0 V or Vcc = 5.0 V Symbol VOH VOL tR tF Pin 12 CRD_VCC - 0.9 0 Min Typ - CRD_VCC 0.4 100 100 V V ns ns Max Unit VOH VOL tR tF 13 CRD_VCC - 0.9 0 CRD_VCC 0.4 100 100 - V V ns ns FCRDCLK FCRDDC tR tF VOH VOL 45 3.15 0 5.0 55 18 18 CRD_VCC +0.5 MHz % ns ns V V FCRDCLK FCRDDC tR tF VOH VOL 14 FIO TRIO TFIO VOH VOL 40 1.85 0 315 5.0 60 18 18 CRD_VCC 0.7 MHz % ns ns V V kHz ms ms V V CRD_VCC - 0.9 0 0.8 0.8 CRD_VCC 0.4 FIO TRIO TFIO VOH VOL RCRDPU TCRDIN TCRDOFF VIHDET VILDET IDET Icrd_iorst Icrd_clk 11 11 11 12, 14 13 14 11 315 0.8 0.8 CRD_VCC 0.4 20 - 50 50 0.70 * Vbat 0 - - - - - 10 - - 150 150 Vbat 0.30 * Vbat - 15 70 26 CRD_VCC - 0.9 0 14 kHz ms ms V V kW ms ms V V mA mA mA 8. The CRD_CLK clock can operate up to 20 MHz, but the rise and fall time are not guaranteed to be fully within the ISO7816 specification over the temperature range. Typically, tr and tf are 12 ns @ CRD_CLK = 10 MHz. http://onsemi.com 11 NCN6000 Programming and Status Functions The NCN6000 features a programming interface and a status interface. Figure 4 illustrates the programming mode. Table 1. Programming and Status Functions Pinout Logic Pins 5 6 3 1 2 7 8 Name STATUS CS PGM A0 A1 RESET I/O (in) CRD_VCC Prg. 3.0 V/5.0 V Not Affected Latch On Rising Edge 0 0/1 0/1 0 0/1 CLOCK_IN Divide Ratio Not Affected Latch On Rising Edge 0 0/1 0/1 0 0/1 CRD_DET Not Affected Latch On Rising Edge 0 0/1 1 1 0/1 CLOCK STOP AND START Not Affected Latch On Rising Edge 0 0/1 0 1 0/1 Poll Card Status READ 0 1 0 0 Z Z DC-DC Status READ 0 1 1 0 Z Z Vbat Status READ 0 1 0 1 Z Z CRD_VCC Status READ 0 1 1 1 Z Z The PGM signal, pin 3, controls the mode of operation (chip programming or smart card transaction) and must be set up accordingly prior to pull Chip Select (pin 6) Low. Table 2. Status Pin Logic Output Name None None CARD PRESENT DC-DC Vbat CRD_VCC Overload CS H L L L L L PGM X L H H H H A1 X X L L H H A0 X X L H L H No Chip Access Programming Mode, No Read Available Low: No Card Inserted High: Card inserted Low: DC-DC Over Range High: DC-DC Operates Normally Low: Vbat Within Range High: Vbat Below Minimum range Low: CRD_VCC Voltage Below Minimum Range High: CRD_VCC in Range Status Logic Level http://onsemi.com 12 NCN6000 Card VCC, Card CLOCK and Card Detection Polarity Programming The CRD_VCC and CLOCK_IN programming options allows matching the system frequency with the card clock frequency, and to select 3.0 V or 5.0 V CRD_VCC supply. The CRD_DET programming option allows the usage of either Normally Open or Normally Close detection switch. Table 3 highlights the A0, A1, PGM and I/O logic states for the possible options. The default power up reset condition is state 1: asynchronous clock, ratio 1/1, CRD_CLK active, CRD_DET = Normally Open, CRD_VCC = 3.0 V. All states are latched for each output variable in programming mode at the positive going slope of Chip Select [CS] signal. It is the system designer's responsibility to set up the options needed to match the chip with the peripherals. In particular, when using Normally Close switch, the CRD_DET polarity must be defined during the first cycles of the initialization. Table 3. Card VCC, Card Clock and Card Detection Polarity Truth Table HEXA $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A $0B $0C $0D $0E $0F $10 $12 $14 $16 CS L L L L L L L L L L L L L L L L L L L L PWR_ON - - - - - - - - - - - - - - - - - 1 - 1 PGM L L L L L L L L L L L L L L L L H H H H RESET L L L L L L L L H H H H H H H H Z Z Z Z A1 L L L L H H H H L L L L H H H H L L H H A0 L L H H L L H H L L H H L L H H L H L H I/O L H L H L H L H L H L H L H L H Z Z Z Z CRD_VCC 3.0 V 3.0 V 3.0 V 3.0 V 5.0 V 5.0 V 5.0 V 5.0 V - - - - - - - - - - - - CRD_CLK CLOCK_IN 1/1 CLOCK_IN 1/2 CLOCK_IN 1/4 CLOCK_IN 1/8 CLOCK_IN 1/1 CLOCK_IN 1/2 CLOCK_IN 1/4 CLOCK_IN 1/8 START STOP Low STOP High Reserve - - - - - - - - CRD_DET - - - - - - - - - - - - Normally Open (Note 12) Normally Close (Note 12) Normally Close (Note 12) Normally Close Note 12) - - - - STATUS H (Note 13) H (Note 13) H (Note 13) H (Note 13) H (Note 13) H (Note 13) H (Note 13) H (Note 13) H (Note 13) H (Note 13) H (Note 13) H (Note 13) H (Note 13) H (Note 13) H (Note 13) H (Note 13) Card Present DC-DC status Vbat CRD_VCC 9. The programmed conditions are latched upon the Chip Select (CS, pin 6) positive going transient. 10. Card clock integrity is guaranteed no spikes whatever be the frequency switching. 11. The STATUS register is not affected when the NCN6000 operates in any of the programming functions. 12. The CRD_VCC and CRD_CLK are not affected when the NCN6000 operates outside their respective decoded logic address. 13. The High Level on STATUS in registers $00 to $0F, inclusive, having being implemented to reduce current consumption but have no other meanings. 14. At turn on, the NCN6000 is initialized with CRD_VCC = 3.0V, CLOCK_IN Ratio = 1/1, CRD_CLK = START, CRD_DET = Normally Open. http://onsemi.com 13 NCN6000 DC-DC Converter and Card Detector Status The NCN6000 status can be polled when CS = L. Please consult Figures 4 and 5 for a description of input and output signals. The status message is described in Table 4. Note: in order to cope with a start up under low battery condition, the Vbat OK message uses a negative logic as depicted here below. Table 4. Card and DC-DC Status Output PGM HIGH HIGH HIGH HIGH HIGH HIGH HIGH HIGH A1 L L L L H H H H A0 L L H H L L H H STATUS LOW HIGH LOW HIGH LOW HIGH HIGH LOW Message No Card Card Present DC-DC Converter Overloaded DC-DC Converter OK Vbat OK Vbat Undervoltage CRD_VCC OK CRD_VCC Undervoltage The STATUS pin provides a feedback related to the detection of the card, the state of the DC-DC converter, the Vbat undervoltage and CRD_VCC undervoltage situations. When PGM = H, the STATUS pin returns a High if a card is detected present, a Low being asserted if there is no card inserted. In any case, the external card is not automatically powered up. When the external MPU asserts PWR_ON = H, together with CS = L, the CRD_VCC supply is provided to the card and the state of the DC-DC converter, the Vbat and the CRD_VCC can be polled through the STATUS pin. Card Power Supply Timing At power up, the CRD_VCC power supply rise time depends upon the current capability of the DC-DC converter associated with the external inductor L1 and the reservoir capacitor connected across CRD_VCC and GROUND. On the other hand, at turn off, the CRD_VCC fall time depends upon the external reservoir capacitor and the peak current absorbed by the internal CMOS transistor built across CRD_VCC and GROUND. These behaviors are depicted in Figure 6. Since these parameters have finite values, depending upon the external constraints, the designer must take care of these limits if the tON or the tOFF provided by the data sheets does not meet his requirements. Typical CRD_VCC Rise Time @ Cout = 10 mF, V = 5.0 V Typical CRD_VCC Fall Time @ Cout = 10 mF, V = 5.0 V Figure 6. Card Power Supply Turn ON and OFF Timing http://onsemi.com 14 NCN6000 Basic Operating Modes Flow Chart The NCN6000 brings all the functions necessary to handle data communication between a host computer and the smart card. The built-in Chip Select pin provides a simple way to share the same MPU bus with several card interface. On top of that, the logic control are derived from specific pins, avoiding the risk of mixing up the operation when the interface is controlled by a low end microcontroller. During the transaction operation, the external MPU takes care of whatever is necessary to he data on the single bidirectional I/O line. Leaving aside the DC-DC control and associated failures, the NCN6000 does not take any further responsibility in the data transaction. When the chip operates in the programming mode, the NCN6000 provide a flexible access to set up the CRD_VCC voltage, the CRD_CLK and the CRD_DET smart card signals. The external microcontroller takes care of the smart card transaction and shall handle the interface accordingly. RESET Vbat = OK STAND BY MODE CS = H PGM = H SELECT OPERATING MODE FINISH CS = H PGM = L CS = L PGM = H CS = L PROGRAMMING MODE ACTIVE MODE PWR_ON = H SET NCN6000 PARAMETERS SEND ATR SEQUENCE LATCH NCN6000 PARAMETERS PGM = H CS = H TRANSACTION MODE END MODE IDLE MODE POWER DOWN SEQUENCE Figure 7. Operating Modes Flow Chart Standby Mode The Standby Mode allows the NCN6000 to detect a card insertion, keeping the power consumption at a minimum. The power supply CRD_VCC is not applied to the card, until the external controllers set PWR_ON = H with CS = L. Standby Mode Logic Conditions: CS PWR_ON A0 A1 PGM I/O RESET =H =H =Z =Z =Z =Z =Z Card Output: CRD_VCC CRD_CLK CRD_RST CRD_IO =0V =L =L =L When a card is inserted, the internal logic filters the signal present pin 11, then asserts the INT pin to Low if the pulse applied to CRD_DET is longer than 150 ms. The external MPU shall run whatever is necessary to handle the card. The INT is cleared (return to High) when a positive going transition is asserted to either the CS or to the PWR_ON signal logically combined with Chip Select = Low. http://onsemi.com 15 NCN6000 Programming Mode The programming mode allows the configuration of the card power supply, card clock and Card Detection input logic polarity. These signals (CRD_VCC, CRD_CLK and CRD_DET) are described in the pin description paragraph associated with Tables 1 and 3 and Figures 4 and 8. Programming Mode Logic Conditions: CS PWR_ON A0 A1 PGM I/O RESET =L =L = H/L = H/L =L = L/H = L/H Card Output: CRD_VCC CRD_CLK CRD_RST CRD_IO =0V =L =L = H/L depending upon the previous I/O pin logic state The I/O and RESET pins are not connected to the smart card and become logic inputs to control the NCN6000 programming sequence. The programmed values are latched upon transition of CS from Low to High, PGM being Low during the transition. When a programming mode is validated by a Chip Select negative going transient, the mode is latched and PGM can be released to High. This latch is automatically reset when CS returns to High. The logic input signals can be set simultaneously, or one bit a time (using either a STAA or a BSET function), the key point being the minimum delay between the shorter bit and the Chip Select pulse. The programmed value is latched into the NCN6000 register on the CS positive going edge. PROGRAMMING PGM I/O A0 A1 RESET CS 2 ms 1 ms 2 ms NORMAL MODE Figure 8. Minimum Programming Timings Active Mode In the active mode, the NCN6000 is selected by the external MPU and the STATUS pin can be polled to get the status of either the DC-DC converter or the presence of the card (inserted or not valid). The power is not connected to the card: CRD_VCC = 0 V. Active Mode Logic Conditions: CS PWR_ON A0 A1 PGM I/O RESET STATUS =L =L =L =L =H =Z =Z = L/H is Card Inserted? Card Output: CRD_VCC CRD_CLK CRD_RST CRD_IO =0V =L =L = H/L depending upon the previous I/O pin logic state The Chip Select pulse [CS] will automatically clear the previously asserted INT signal upon the positive going transition. If a card is present, the MPU shall activate the DC-DC converter by asserting PWR_ON = H. The NCN6000 will automatically run a power up sequence when the CRD_VCC reaches the undervoltage level (either VC5H or VC3H, depending upon the CRD_VCC voltage supply programmed). The CRD_IO, CRD_RST and CRD_CLK pins are validated, according to the ISO7816-3 sequence. The interface is now in transaction mode and the system is ready for data exchange through the I/O and RESET lines. At any time, the microcontroller can change the CRD_CLK frequency and mode, or the CRD_VCC value as determined by the card being in use. http://onsemi.com 16 NCN6000 Transaction Mode During the transaction mode, the NCN6000 maintains power supply and clock signal to the card. All the signal levels related with the card are translated as necessary to cope with the MPU and the card. The DC-DC converter status and the Vbat state can be monitored on the STATUS by using the A0 and A1 logic inputs as depicted in Tables 3 and 4. Transaction Mode Logic Conditions: CS PWR_ON A0 A1 PGM I/O RESET STATUS =L =H =H =H =H = DATA TRANSFER = H/L = L/H DC-DC status: Fail/Pass? Card Output: CRD_VCC CRD_CLK CRD_RST CRD_IO = 3.0 or 5.0 V = CLOCK = H/L = DATA TRANSFER In addition, the CRD_CLK signal can be stopped, as depicted in Tables 3 and 4, to minimize the current consumption of the external smart card, leaving CRD_VCC active. Power Down Operation The power down mode can be initiated by either the external MPU (pulling PWR_ON = L) or by one of the internal error condition (CRD_VCC overload or Vbat Low). The communication session is terminated immediately, according to the ISO7816-3 sequence. On the other hand, the MPU can run the Standby mode by forced CS = H. When the card is extracted, the interface shall detect the operation and run the Power Shut Off of the card as described by the ISO/CEI 7816-3 sequence depicted here after: ISO7816-3 sequence: Force RST to Low Force CLK to Low, unless it is already in this state Force CRD_IO to Low Shut Off the CRD_VCC supply Since the internal digital filter is activated for any card insertion or extraction, the physical power sequence will be activated 150 ms maximum after the card has been extracted. Of course, such a delay does not exist when the MPU launch the power down intentionally. The time delay between each negative going signal is 500 ns typical (Figure 10). To make sure the data are not polluted by power losses, it is recommended to check the state of CRD_VCC before launching a new data transaction. Since CS = L, this is achieved by forcing bits A0 and A1 according to Table 4, and reading the STATUS pin 5. Idle Mode The idle mode is used when a card is powered up (CRD_VCC = Vcc), without communication on going. Idle Mode Logic Conditions: CS PWR_ON A0 A1 PGM I/O RESET STATUS =L =H =H =H =H =Z =H = L/H according to the internal register results Card Output: CRD_VCC = 3.0 or 5.0 V CRD_CLK = CLOCK active or L or H CRD_RST = H CRD_IO = Z http://onsemi.com 17 NCN6000 CARD EXTRACTION DETECTED CRD_VCC Voltage CRD_CLK CRD_RST CRD_IO Digital Filter Delay (50 ms min) Figure 9. Typical Power Down Sequence in the NCN6000 Interface CRD_VCC CRD_RST CRD_CLK CRD_IO Figure 10. Power Down Sequence Details http://onsemi.com 18 NCN6000 Card Detection The card detector circuit provides a 500 kW pull up resistor to bias the CRD_DET pin, yielding a logic High when the pin is left open (assuming a NO switch). The internal logic associated with pin 11 provides an automatic selection of the slope card detection, depending upon the polarity set by the external MPU. At start up, the CRD_DET is preset to cope with Normally Open switch. When a Normally Close switch is used in the card socket, it is mandatory to program the NCN6000 chip during the initialization sequence, otherwise the system will not start if a card was previously inserted. Table 3 gives the programming code for such a function. The next lines provide a typical assembler source to handle this CRD_DET Normally Close polarity: Smart EQU LDX LDAA STAA $20 #$1000 #$09 smart, X ; NCN6000 Physical CS Address ; Offset ; I/O = H, A0 = A1 = L, RESET = H ; Set CRD_DET = Normally Closed Switch The CRD_DET polarity can be updated at any time, during the Program Mode sequence (PGM = L), but, generally speaking, is useless since the switch does not change during the usage of the considered module. On the other hand, the card detection switch shall be connected across pin 11 and ground, for any polarity selected. The transition presents pin 11, whatever be the polarity, is filtered out by the internal digital filter circuit, avoiding false interrupt. In addition to the minimum internal 50 ms timing, the MPU shall provide an additional delay to cope with the mechanical stabilization of the card interface (typically 3 ms), prior to valid the CRD_VCC supply. When a card is inserted, the detector circuit asserts INT = Low as depicted before. When the NCN6000 detects a card extraction, the power down sequence is activated, regardless of the PWR_ON state, and the INT pin is asserted Low. It is up to the external MPU to clear this interrupt by forcing a chip select pulse as depicted in Figure 5. The 75 ms delay represent the digital filter built-in the NCN6000 chip being used for the characterization. Any pulse shorter than this delay does not generate an interrupt. However, to guarantee an interrupt will be generated, the CRD_DET signal must be longer than 150 ms as defined by the specification. The Chip Select pulse is generated by the external microcontroller, the minimum pulse width being 2 ms to make sure the card is detected. The oscillogram, Figure 11, depicts the behavior for a Normally Open switch, the delay existing between the interrupt negative going state and the CS being Low comes from the particular software latency existing in this particular MPU. Digital Filter Delay INTERRUPT Chip Select Acknowledge or Clear Interrupt Figure 11. Card Insertion Detection and Interrupt Signals http://onsemi.com 19 NCN6000 CRD_DET Input Voltage (card extracted) Digital Filter Delay INTERRUPT Chip Select Acknowledge or Clear Interrupt Figure 12. Card Extraction Detection and Interrupt Signals When the card is extracted, the CRD_DET signal generates an interrupt, assuming the positive pulse width is longer than the digital filter. The oscillogram, Figure 12, depicts the behavior for a Normally Open switch. Note: since the internal pull up resistor is relatively high (500 kW typical), one must use a 10 MW input impedance probe to read this signal. CRD_DET Input Voltage (card inserted) INTERRUPT Chip Select Figure 13. Interrupt Acknowledgement During a Card Insertion Detection Sequence The interrupt signal, provided pin 9, is cleared by a positive going Chip Select signal as depicted by the oscillogram, Figure 13. The CS pulse width is irrelevant, as long as it is larger than 2.0 ms, to activate a different sequence. Leaving the interrupt signal Low has no influence on the internal behavior of the NCN6000, but will be automatically cleared when the DC-DC will be activated by the MPU (CS=L, PWR_ON = Positive High transition) http://onsemi.com 20 NCN6000 Power Management The purpose of the power management is to activate the circuit functions needed to run a given mode of operation, yielding a minimum current consumption on the Vbat supply. In the Standby mode (PWR_ON = L), the power management provides energy to the card detection circuit only. All the card interface pins are forced to ground potential. In the event of a power up request coming from the external MPU (PWR_ON = H, CS = L), the power manager starts the DC-DC converter. When the CRD_VCC voltage reaches the programmed value (3.0 V or 5.0 V), the circuit activates the card signals according to the following sequence: CRD_VCC CRD_IO CRD_CLK CRD_RST The logic level of the data lines are asserted High or Low, depending upon the state forced by the external MPU, when the start up sequence is completed. Under no situation the NCN6000 shall launch automatically a smart card ATR sequence. Assuming PWR_ON = H, the CRD_VCC voltage is maintained whatever be the logic level presents on Chip Select, pin 6. At the end of the transaction, asserted by the MPU (PWR_ON = L, CS = L), or under a card extraction, the ISO7816-3 power down sequence takes place: CRD_RST CRD_CLK CRD_IO CRD_VCC When CS = H, the bi-directional I/O line (pins 8 and 15) is forced into the High impedance mode to avoid signal collision with any data coming from the external MPU. The CRD_VCC voltage is controlled by means of CS and PWR_ON logic signal as depicted in Figure 14. The PWR_ON logic level define the CRD_VCC voltage status, the amplitude being the one pre programmed into the chip. In order to avoid uncontrolled command applied to the smart card, the NCN6000 internal logic circuit, together with the Vbat monitoring, clamps the card outputs until the CRD_VCC voltage reaches the minimum value. During the CRD_VCC slope, all the card outputs are kept Low and no spikes can be write to the smart card. The oscillogram on the right hand side is a magnification of the curves given on the opposite side. CS PWR_ON CRD_VCC 2 ms CRD_VCC Rise Time CRD_VCC No Change CRD_VCC Power Down Fall Time CRD_VCC No Change 250 ms Figure 14. Card Power Supply Control 5.0 V CRD_VCC 5.0 V CRD_VCC CRD_RST CRD_RST CRD_CLK CRD_CLK CP = 15 pF CP = 15 pF CRD_IO CRD_IO Figure 15. Smart Card Signals Sequence at Power On http://onsemi.com 21 NCN6000 Vbat Supply Voltage Monitoring The built-in comparator, associated with the band gap reference, continuously monitors the +Vbat input. During the start up, all the NCN6000 functions are deactivated and no data transfer can take place. When the +Vbat voltage rises above 2.35 V (typical), the chip is activated and all the functions becomes available. The typical behavior is provided here after Figure 16. At this point, the internal Power On Reset signal is activated (not accessible externally) and all the logic signals are forced into the states as defined by Table 3. If the +Vbat voltage drops below 2.25 V (typical) during the operation, the NCN6000 generate a Power Down sequence and is forced in a no operation mode. The built-in 100 mV (typical) hysteresis avoids unstable operation when the battery voltage slowly varies around the 2.30 V. On the other hand, the microcontroller can read the STATUS signal, pin 5, to control the state of the battery prior to launch either a NCN6000 programming or an ATR sequence (Table 4). 3.30 V 2.80 V 2.35 V 2.25 V Vbat Vbat_OK Vbat STATUS Note: Drawing is not to scale and voltages are typical. See specifications data for details. Figure 16. Typical Vbat Monitoring DC-DC Converter Operation The built-in DC-DC converter is based on a modified boost structure to cover the full battery and card operating voltage range. The built-in battery voltage monitor provides an automatic system to accommodate the mode of operation whatever be the Vbat and CRD_VCC voltages. Comparator U3/Figure 17 tracks the two voltages and set up the operating mode accordingly. Vbat 20 Vbat Current Sense Vbat U1 + - R1 1R 19 Lout_H L2 22 mH 18 15 Lout_L CRD_VCC C1 R2 + - U3 Vbat/VCC Comparator GND + GND PWR_ON LOGIC CONTROL 3 V/ 5 V Overload VCC_OK MOS Drive Substrat Bias NMOS Gate Drive Q1 GND Vbat Voltage Regulation - U2 + GND GND GND R3 Q4 Q2 GND PMOS Gate Drive Vref Q3 R4 GND Vref_3/5 V Vout_3_5 Active Pull Down 17 PWR_GND Figure 17. Basic DC-DC Structure http://onsemi.com 22 NCN6000 When the input voltage Vbat is lower than the programmed CRD_VCC, the system operates under the boost mode, providing the voltage regulation and current limit to the smart card. In this mode, the external inductor, typically 22 mH, stores the energy to drive the +5.0 V card supply from the external low voltage battery. The oscillogram, Figure 18, depicts the DC-DC behavior under these two modes of operation. Beside the DC-DC converter, NMOS Q4 provides a low impedance to ground during the Power Down sequence, yielding the 250 ms maximum switch time depicted in the data sheet. 8 POWER_ON 7 -25C 6 Ibat_op (mA) Ibat 5 4 3 2 1 CRD_VCC 0 2.5 Step Down Mode CRD_VCC 5 V Step Up Mode 3.0 3.5 4.0 4.5 5.0 5.5 6.0 Vbat (V) DC Operating Current @ CRD_VCC = 5.0 V 85C 25C IL Figure 18. DC-DC Operating Modes Figure 19. Typical DC Operating Current When the input voltage Vbat is higher than the programmed CRD_VCC, the system operates under a step down mode, yielding the voltage regulation and current limit identical to the boost mode. In this case, the built-in structure turns Off Q1 and inverts the Q2 substrate bias to control the current flowing to the load.These operations are fully automatic and transparent for the end user. The High and Low limits of the current flowing into the external inductor L1 are sensed by the operational amplifier U1 associated with the internal shunt R1. Since this shunt resistor is located on the hot side of the inductor, the device reads both the charge and discharge of the inductor, providing a clean operation of the converter. In order to optimize the DC-DC power conversion efficiency, it is recommended to use external inductor with R < 2.0 W. The output capacitor C1 stores the energy coming from the converter and smooths the CRD_VCC voltage applied to the external card. At this point, care must be observed, beside the micro farad value, to select the right type of capacitor. According to the capacitor's manufacturers, the internal ESR can range from a low 10 mW to more than 3.0 W, thus yielding high losses during the DC-DC operation, depending upon the technology used to build the capacitor. The standard electrolytic capacitors have the low cost advantage for a relative high micro farad value, but have poor tolerance, high leakage current and high ESR. The tantalum type brings much lower leakage current together with high capacity value per volume, but cost can be an issue and ESR is rarely better than 500 mW. The new ceramic type have a very low leakage together with ESR in the 50 mW range, but value above 10 mF are relatively rare. Moreover, depending upon the low cost ceramic material used to build these capacitors, the thermal coefficient can be very bad, as depicted in Figure 20. The X7R type is highly recommended to achieve low voltage ripple. 100% 15% -25C +25C +85C Figure 20. Typical Y7R Ceramic Type Value as a Function of the Temperature. http://onsemi.com 23 NCN6000 Based on the experiments carried out during the NCN6000 characterization, the best comprise, at time of printing this document, is to use two 6.8 mF/10 V/Ceramic/X7R capacitor in parallel to achieve the CRD_VCC filtering. The ESR will not extend 50 mW over the temperature range and the combination of standard parts provide an acceptable -20% to +20% tolerance, Table 5. Ceramic/Electrolytic Capacitors Comparison Manufacturers MURATA VISHAY VISHAY Type/Series CERAMIC/GRM225 Tantalum/594C/593C Electrolytic/94SV Electrolytic Low Cost Format 0805 Max Value 10 mF/6.3 V 10 mF/16 V 10 mF/10 V 10 mF/10 V -20%/+20% -35%/+50% Tolerance +80%/-20% Typ. Z @ 500 kHz 30 mW 450 mW 400 mW 2.0 W together with a low cost. Obviously, the capacitor must be SMD type to achieve the extremely low ESR and ESL necessary for this application. Figure 21 illustrates the CRD_VCC ripple observed in the NCN6000 demo board depending upon the type of capacitor used to filter the output voltage. C= 10 mF Electrolytic or Tantalum C= 10 mF Ceramic Top Trace = Electrolytic or Tantalum 10 mF Bottom Trace = X7R 10 mF ceramic The high ripple pulse across CRD_VCC is the consequence of the large ESR of the electrolytic capacitor. Figure 21. CRD_VCC Ripple as a Function of the Capacitor Technology NOTES: Rload = 100 W , Vbat = 5.0 V, CRD_VCC = 5.0 V Cout = 10 mF/X7R, CRD_CLK = Stop High Figure 22. External Capacitor Current Charge and CRD_VCC Voltage Ripple. Figure 23. CRD_VCC Voltage Ripple http://onsemi.com 24 NCN6000 Clock Divider The main purpose of the built-in clock generator is threefold: 1. Adapts the voltage level shifter to cope with the different voltages that might exist between the MPU and the Smart Card. 2. Provides a frequency division to adapt the Smart Card operating frequency from the external clock source. 3. Controls the clock state according to the smart card specification. In addition, the NCN6000 adjusts the signal coming from the microprocessor to get the Duty Cycle window as defined by the ISO7816-3 specification. The logic input pins A0, A1, PGM, I/O and RESET fulfill the programming functions when both PGM and CS are CLOCK_IN 1 2 1 2 3 3 Low. The clock input stage (CLOCK_IN) can handle a 40 MHz frequency maximum, the divider being capable to provide a 1:8 ratio. Of course, the ratio must be defined by the engineer to cope with the Smart Card considered in a given application and, in any case, the output clock [CRD_CLK] shall be limited to 20 MHz maximum signal. In order to maximize the CLOCK_IN bandwidth, this pin has no Schmitt trigger input. The simple associated CMOS has a Vbat/2 threshold level. In order to minimize the dI/dt and dV/dV developed in the CRD_CLK line, the peak current as been internally limited to 30 mA peak (typical @ CRD_VCC = 5.0 V), hence limited the rise and fall time to 10 ns typical. Consequently, the NCN6000 fulfills the ISO7816 specification up to 10 MHz maximum, but can be used up to 20 MHz when the final application operates in a limited ambient temperature range. CS 3 CRD_VCC RESET 3 PGM Clock & VCC Programming Block Level Shifter & Control CRD_CLK I/O A0 A1 +3.0 V +5.0 V Figure 24. Simplified Frequency Divider and Programming Functions In order to avoid any duty cycle out of the frequency smart card ISO7816-3 specification, the divider is synchronized by the last flip flop, thus yielding a constant 50% duty cycle, whatever be the divider ratio. Consequently, the output CRD_CLK frequency division can be delayed by eight CLOCK_IN pulses and the microcontroller software must take this delay into account prior to launch a new data transaction. http://onsemi.com 25 NCN6000 The example given by the oscillogram here above highlights the delay coming from the internal clock duty cycle resynchronization. In this example, the clock is internally divided by 2 prior to be applied to the CRD_CLK pin. Since the clock signal is asynchronous, it is up to the programmer to make sure the next card transaction is not activated before the CRD_CLK signal has been updated. Generally speaking, such a delay can be derived from the maximum clock frequency provided to the interface, keeping in mind the maximum delay is eight incoming clock pulses. Figure 25. Clock Programming Examples The clock can be re-programmed without halting the rest of the circuit, whatever be the new clock divider ratio. In particular, the CRD_VCC can be applied to the card while the clock is re-programmed. http://onsemi.com 26 NCN6000 Figure 26. Command Stop Clock HIGH The CRD_CLK signal is halted in the High logic state, following the Chip Select positive going transition. Logic Input conditions: PGM = Low RESET = Low I/O = Low A0 = Low A1 = Low CS = Low pulsed Figure 27. Command Stop Clock LOW The CRD_CLK signal is halted in the Low logic state, following the Chip Select positive going transition. Logic Input conditions: PGM = Low RESET = Low I/O = High A0 = Low A1 = Low CS = Low, pulsed http://onsemi.com 27 NCN6000 Figure 28. Command Resume Clock Normal Operation The CRD_CLK signal is resumed in the normal operation, following the Chip Select positive going transition. The previous halted state is irrelevant and the clock signal is synchronized with the internal clock divider to avoid non CRD_CLK 50% duty cycle. PGM = Low RESET = High I/O = Low A0 = Low A1 = Low CS = Low, pulsed CRD_CLK C3 Rise 7.900 ns Cp = 30 pF CRD_CLK C3 Fall 8.255 ns Cp = 30 pF Figure 29. Card Clock Rise and Fall Time Since the CRD_CLK signal can generate very fast transient (i.e. tr = 2.5 ns @ Cp = 10 pF), adapting the design to cope with the EMV noise specification might be necessary at final check out. Using an external RC network is a way to reduce the dv/dt, hence the EMI noise. Typically, the external series resistor is 10 W, the total capacitance being 30 pF to 50 pF http://onsemi.com 28 NCN6000 Bidirectional Level Shifter The NCN6000 carries out the voltage difference between the MPU and the Smart Card I/O signals. When the start sequence is completed, and if no failures have been detected, the device becomes essentially transparent for the data transferred on the I/O line. To fulfill the ISO7816-3 specification, both sides of the I/O line have built in pulsed circuitry to accelerate the signal rise transient. The I/O line is connected on both side of the interface by a NMOS switch which provide the level shifter and, due to its relative high internal impedance, protects the Smart Card in the event of data collision. Such a situation could occurs if either the MPU of the smart card forces a signal in the opposite logic level direction. When the CS signal goes High, or if the MPU is running any of the programming functions, the built in register holds the previous state presents on the input I/O pin. This mechanism is useful to force the CRD_IO card pin in either a High or a Low pre-defined logic state. It is the responsibility of the programmer to set up the I/O line according to the system's activity Device Q4 provides a low impedance to ground when the CRD_IO line is deactivated. This mechanism avoids noise presence on this line during any of the power operation. When either side of this level shifter is forced to Low, the externally connected device will be forward biased by the DC current flowing through the pull up resistors as depicted in Figure 30. Since these two resistors will carry 350 mA max each under the worst case conditions, care must be observed to make sure the external device will be capable to handle this level of current. Note: the typical series impedance of the internal MOS device (Q3, Figure 30) is 400 W. The oscillograms in Figure 31 give the worst case operation when the stray capacitance is 15 pF. Vbat CRD_VCC Q1 20 k 200 ns I/O 200 ns Q2 20 k I/O CRD_IO Q3 Q4 CRD_IO CARD ENABLE Seq 1 LOGIC GND CRD_VCC = 5.0 V Figure 30. Basic Internal I/O Level Shifter Figure 31. Typical CRD_IO Rise Time CRD_VCC CRD_VCC = 3.0 V I/O Card Answer Request Sends on CRD_RST Line NCN6000 Chip Select Note: The I/O data depends solely upon the smart card ATR content, the NCN6000 being not involved in these data. Figure 32. Typical I/O and RST Signals During an ATR Sequence. http://onsemi.com 29 NCN6000 Input Schmitt Triggers All the Logic Input pins have built-in Schmitt trigger circuits to prevent the NCN6000 against uncontrolled operation. The typical dynamic characteristics of the related pins are depicted in Figure 33. The output signal is guaranteed to go High when the input voltage is above 0.70*Vbat, and will go Low when the input voltage is below 0.30*Vbat. Output The CLOCK_IN pin has been design to provide a 40 MHz bandwidth clock receiver input, capable to drive the internal clock divider. This front end circuit yields a constant Duty Cycle signal, according to the ISO specification, to the external smart card, even when the NCN6000 division ratio is 1:1. Vbat ON OFF Input 0.30 *Vbat 0.70 *Vbat Vbat Figure 33. Typical Schmitt Trigger Characteristic Interrupt Function The NCN6000 flags the external microprocessor by pulling down the INT signal provided in pin 9. This signal is activated by one of the here below referenced operations. Table 6. Interrupt Functions Pin Related Card Insertion and Extraction DC-DC Converter Overloaded 11 Clear Function Positive Going Chip Select, or logical combination of Chip Select Low and PWR_ON Positive Going Positive Going Chip Select, or logical combination of Chip Select Low and PWR_ON Positive Going STATUS Pin 5 High = Card Presents Low = No Card Inserted High = DC-DC Operates Normally Low = Output CRD_VCC Overloaded 15 Leaving the INT pin Low has no influence on the NCN6000 internal behavior. It is up to the engineering to decide when and how the interrupt will be cleared from this pin. As described before, this can be achieved by either providing a Chip Select positive transient, or by starting the DC-DC converter with the standard command PWR_ON = H and CS =L. http://onsemi.com 30 NCN6000 Security Features In order to protect both the interface and the external smart card, the NCN6000 provides security features to prevent catastrophic failures as depicted here after. Pin Current Limitation: In the case of a short circuit to ground, the current forced by the device is limited to 15 mA for any pins, except CRD_CLK pin. No feedback is provided to the external MPU. DC-DC Operation: The internal circuit continuously senses the CRD_VCC voltage and, in the case of either over or undervoltage situation, update the STATUS register accordingly. This register can be read out by the MPU. Battery Voltage: Both the Over and Undervoltage are detected by the NCN6000, a POWER_DOWN sequence and the STATUS register being updated accordingly. The external MPU can read the STATUS pin to take whatever is appropriate to cope with the situation. ESD Protection The NCN6000 includes silicon devices to protect the pins against the ESD spikes voltages. To cope with the different ESD voltages developed across these pins, the built-in structures have been designed to handle either 2.0 kV, when related to the microcontroller side, or 8.0 kV when connected with the external contacts. Practically, the CRD_RST, CRD_CLK, CRD_IO and CRD_DET pins can sustain 8 kV, the digital pins being capable to sustain 2 kV. The CRD_VCC pin has the same 8 kV ESD protection, but can source up to 55 mA continuously, the absolute maximum current being 100 mA. To save as much battery current as possible when no card is inserted, one should use a Normally Open Card Detection switch connected pin 11. Since the internal card detection circuit source 10 mA (typical) to bias the switch, using a Normally Open avoid this direct sink to ground from the battery. Parallel Operation When two or more NCN6000 operate in parallel on a common digital bus, the Chip Select pin allows the selection of one chip from the bank of the paralleled devices. Of course, the external MPU shall provide one unique CS line for each of the NCN6000 considered interfaces. When a given interface is selected by CS = L, all the logic inputs becomes active, the chip can be programmed or/and the external card can be accessed. When CS = H, all the input logic pins are in the high impedance state, thus leaving the bus available for other purpose. On the other hand, when CS = H, the CRD_IO and CRD_RST hold the previous I/O and RESET logic state, the CRD_CLK being either active or stopped, according to the programmed state forced by the MPU. Since there is one single I/O line to communicate with the external microcontroller, one should provide a software routine to save the code when data exchanged are performed between the two cards. Generally speaking, the internal microcontroller RAM can be used to support such a transaction. The CRD_VCC voltage and CRD_CLK signal of each NCN6000 can be operated simultaneously, these two pins being activated even when the related chip select is High. As depicted in Figure 14, the DC-DC converter is not deactivated when PWR_ON goes to Low when CS = High. Minimum Power Consumption To achieve a minimum current consumption, the interface shall be programmed as follow: 1. Turn off the DC-DC converter : this will disconnect the smart card if still inserted in the socket), reducing the power supply to the minimum needed to control the interface. 2. Force the input signals to a logic High to avoid current flowing through the pull up resistors. This applies to the here below table: INT CS STATUS I/O CRD_IO Pin 9 Pin 6 Pin 5 Pin 8 Pin 14 To save as much battery current as possible when no card is inserted, one should use a Normally Open Card Detection switch connected pin 11 to ground. Since the internal card detection circuit source is 10 mA (typical), using such a NO switch saves the direct sink to ground current from the battery to ground. During this mode of operation, the only active sub functions are the card detection and the battery monitoring. The activity resume immediately after either a card insertion, or a CS = Low signal applied to pin 6. http://onsemi.com 31 NCN6000 Printed Circuit Board Layout Since the NCN6000 carries high speed currents together with high frequency clock, the printed circuit board must be carefully designed to avoid the risk of uncontrolled operation of the interface. A typical single-sided PCB layout is provided in Figure 34 highlighting the ground technique. The card socket uses a low cost ISO only version, all the parts being located on the Component side. Connector J3 makes reference to the microcontroller used by the final application. Of course, the connector is not necessary and standard copper tracks might be used to connect the MPU to the NCN6000 interface chip. 2335 mis (60 mm) MPU SMARTCARD ISO CONTACTS U1 NCN6000 2760 mis (70 mm) RST Vsupply +Vbat C4 CLK C8 I/O VPP GND GROUND Figure 34. Typical Single Sided Printed Circuit Board Layout Application Note A partial schematic diagram of the demo board designed to support the NCN6000 applications is depicted in Figure 35. This schematic diagram highlights the interface between the microcontroller and the Smart Card, leaving aside the peripherals used to control the MPU. Conclusion From a practical stand point, the CRD_VCC output capacitor has been split into two 6.8 mF/10 V/X7R, one being located as close as possible across pins 13 and 17 of the NCN6000, the second one being located close by the smart card physical connector. On the other hand, care has been observed to minimize the cross coupling between the clock signals (both Input and CRD_CLK) and the other signals presents on the board. The microcontroller holds the software necessary to program the NCN6000, together with the code handling the T0 operation. Provisions are made to provide a communication link with an external computer by using the RS232 standard port. Due to the Chip Select signal, several NCN6000 can share a common data bus as depicted in Figure 36. In this example, two interfaces are connected to a single MPU, the CS pins being controlled by two different signals. http://onsemi.com 32 NCN6000 VCC C1 10 mF/6.3 V C2 GND 0.1 mF/25 V R6 10 M VCC 8 XTAL R1 10k C1 0.1 mF/25 V 1 3 2 6 5 4 9 10 11 12 13 14 15 16 I/O A0 A1 RESET PGM PWR_ON CS R7 4.7k VCC INT CLK C2 GND 10 mF/6.3 V 1 2 3 4 5 6 7 8 9 10 A0 A1 PGM PWR_ON STATUS CS RESET I/O INT CLOCK_IN Lout_L PWR_GND GROUND CRD_VCC 15 14 CRD_IO 13 CRD_CLK 12 CRD_RST 11 CRD_DET 18 17 16 GND U1 Vbat Lout_H 20 19 L1 22 mH 26 VDD 34 PA0 33 PA1 32 PA2 31 PA3 PA4 PA5 PA6 PA7 PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PB7 PB6 PB5 PB4 PB3 PB2 MODA STRB STRA PB1 PB0 VCC R9 4.7k RST U1 68HC11E9 VCC 1 RESET 3 GND VCC R16 220 R R16 220 R SW13 RESET C11 2.2 mF 16 V GND IN 2 R21 4.7 k U5 MC34164 SW DIP-2 1 = Mode B 2 = Mode A GND R20 4.7 k RX C6 22 pF GND GND C7 22 pF Y1 8 MHz VCC 7 EXTAL 29 28 27 30 43 45 47 49 44 46 48 50 35 36 37 38 39 40 41 42 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 20 XIRQ 19 IRQ 5 E 20 PD0/RXD 21 PD1/TD 22 PD2 23 PD3 24 PD4 25 STATUS PD5 VCC R8 4.7k C4 0.1 mF/25 V NCN6000 J2 ISO7816 C8 VCC R10 4.7k I/O VPP GND C4 CLK RST VCC Swb Swa TX 8 7 6 5 4 3 2 1 18 17 GND C9 4.7 mF/10 V GND 1 VSS 51 VRL 52 VRH 2 MODB 3 17 R14 10 R 6 4 S? SMARTCARD_B C10 4.7 mF/10 V GND GND Figure 35. NCN6000 Single Interface Demo Board http://onsemi.com 33 NCN6000 VCC C1 10 mF/6.3 V C2 GND 0.1 mF/25 V C1 R6 10 M VCC 8 XTAL R2 10k 0.1 mF/25 V 1 4 3 2 6 5 9 10 11 12 13 14 15 16 I/O A0 A1 RESET PGM PWR_ON CS C2 GND 1 2 3 4 5 6 7 8 9 A0 A1 PGM PWR_ON STATUS CS RESET I/O Lout_L PWR_GND GROUND CRD_VCC 15 18 17 16 GND U1 NCN6000 Vbat Lout_H 10 mF/6.3 V 20 19 L1 22 mH 26 34 PA0 33 PA1 32 PA2 PA3 PA4 PA5 PA6 PA7 PE0 PE1 PE2 PE3 PE4 PE5 PE6 PE7 PB7 PB6 PB5 PB4 PB3 PB2 MODA STRB STRA PB1 PB0 VCC R4 4.7k RST U1 68HC11E9 VCC 17 1 3 RESET GND GND R16 220 R R16 220 R IN 2 R10 4.7 k U5 MC34164 C11 2.2 mF 16 V SW DIP-2 1 = Mode B 2 = Mode A R9 4.7 k SW13 RESET C10 4.7 mF/10 V GND 31 7 C6 22 pF GND Y1 8 MHz GND C7 22 pF VCC VDD EXTAL 29 28 27 30 43 45 47 49 44 46 48 50 35 36 37 38 39 40 41 42 PC0 PC1 PC2 PC3 PC4 PC5 PC6 PC7 XIRQ IRQ 20 R5 4.7k 19 VCC INT ISO7816 SMARTCARD_B 5 E 20 PD0/RXD 21 PD1/TD 22 PD2 23 PD3 24 PD4 25 PD5 STATUS VCC R6 4.7k VCC R7 4.7k 14 CRD_IO 13 CRD_CLK INT 12 CRD_RST 10 11 CLOCK_IN CRD_DET J2 8 7 6 5 4 C4 CLK RST VCC Swb Swa 3 2 1 18 17 GND GND CLK 10 9 8 8 7 6 5 4 4 3 2 1 GND C8 I/O VPP GND 1 VSS 51 VRL 52 VRH 2 MODB 3 R8 10 R S1 6 4 C5 0.1 mF/25 V RX TX GND J2 ISO7816 SMARTCARD_B GND VCC VPP RST Swa 17 Swb CLK I/O C4 C8 20 A0 Vbat bat U1 19 A1 Lout_H out_H NCN6000 PGM 18 Lout_L PWR_ON PWR_ON out_L 17 STATUS STATUS PWR_GND 16 CS GROUND 15 RESET CRD_VCC CC 14 I/O I/O CRD_IO CRD_IO 13 CRD_CLK CRD_CLK INT 12 CRD_RST 11 CLOCK_IN CLOCK_IN CRD_DET CRD_DET 18 1 2 3 4 GND 5 6 7 8 L1 22 mH C9 4.7 mF/10 V GND Figure 36. NCN6000 Single Interface Demo Board http://onsemi.com 34 NCN6000 Summary Subject PIN FUNCTIONS AND DESCRIPTION MAXIMUM RATINGS POWER SUPPLY SECTION DIGITAL PARAMETERS SECTION SMART CARD INTERFACE SECTION PROGRAMMING AND STATUS FUNCTIONS CARD VCC, CARD CLOCK AND CARD DETECTION POLARITY PROGRAMMING DC-DC CONVERTER AND CARD DETECTOR STATUS CARD POWER SUPPLY TIMINGS BASIC OPERATING MODE FLOW CHART STANDBY MODE PROGRAMMING MODE ACTIVE MODE TRANSACTION MODE IDLE MODE CARD POWER DOWN MODE CARD DETECTION POWER MANAGEMENT VBAT SUPPLY VOLTAGE MONITORING DC-DC CONVERTER OPERATION CLOCK DIVIDER BIDIRECTIONNAL LEVEL SHIFTER INPUT SCHMITT TRIGGERS INTERRUPT FUNCTIONS SECURITY FEATURES ESD PROTECTION MULTI CARD PARALLEL OPERATION MINIMUM POWER CONSUMPTION PRINTED CIRCUIT BOARD LAYOUT APPLICATION NOTE PACKAGE OUTLINE DIMENSIONS CONCLUSION Page 6 8 9 10 11 12 13 7 14 14 15 15 16 16 17 17 17 19 21 22 22 25 29 30 30 31 23 31 31 31 32 32 36 32 25 26 27 28 29 30 31 32 33 34 35 36 24 22 13 14 15 16 17 18 19 20 21 10 11 12 8 9 Figure Index Fig. # 1 2 3 4 5 6 Title Simplified Application Diagram Typical Application Diagram Block Diagram Programming and Normal Operation Basic Timing Interrupt Servicing and Card Polling Card Power Supply Turn ON and OFF Timing Operating Modes Flow Chart Minimum Programming Timings Typical Power Down Sequence in the NCN6000 Interface Power Down Sequence Details Card Insertion Detection and Interrupt Signals Card Extraction Detection and Interrupt Signals Interrupt Acknowledgement during a Card Insertion Detection Sequence. Card Power Supply Control Smart Card Signals Sequence at Power On Typical Vbat Monitoring Basic DC-DC Structure DC-DC Operating Modes Typical DC Operating Current Typical Y7R Ceramic Type Value as a Function of the Temperature. CRD_VCC Ripple as a Function of the Capacitor Technology External Capacitor Current Charge and CRD_VCC Voltage Ripple CRD_VCC Voltage Ripple Simplified Frequency Divider and Programming Functions Clock Programming Examples Command Stop Clock HIGH Command Stop Clock LOW Command Resume Clock Normal Operation Card Clock Rise and Fall Time Basic internal I/O Level Shifter Typical CRD_IO Rise Time Typical I/O and RST Signals During an ATR Sequence Typical Schmitt Trigger Characteristic Typical Single Sided Printed Circuit Board Layout NCN6000 Single Interface Demo Board Typical Dual Interface Application Page 1 2 3 4 5 14 15 16 18 18 19 20 20 21 21 22 22 23 23 23 24 24 24 25 26 27 27 28 28 29 29 29 30 32 33 34 http://onsemi.com 35 NCN6000 PACKAGE DIMENSIONS TSSOP-20 DTB SUFFIX CASE 948E-02 ISSUE B 20X K REF M 0.15 (0.006) T U S 0.10 (0.004) TU S V S 2X L/2 L PIN 1 IDENT 1 10 B -U- J J1 N 0.15 (0.006) T U S A -V- N F C D 0.100 (0.004) -T- SEATING PLANE G H DETAIL E ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner. PUBLICATION ORDERING INFORMATION LITERATURE FULFILLMENT: N. American Technical Support: 800-282-9855 Toll Free Literature Distribution Center for ON Semiconductor USA/Canada P.O. Box 61312, Phoenix, Arizona 85082-1312 USA Phone: 480-829-7710 or 800-344-3860 Toll Free USA/Canada Japan: ON Semiconductor, Japan Customer Focus Center 2-9-1 Kamimeguro, Meguro-ku, Tokyo, Japan 153-0051 Fax: 480-829-7709 or 800-344-3867 Toll Free USA/Canada Phone: 81-3-5773-3850 Email: orderlit@onsemi.com ON Semiconductor Website: http://onsemi.com Order Literature: http://www.onsemi.com/litorder For additional information, please contact your local Sales Representative. http://onsemi.com 36 IIII IIII IIII SECTION N-N M DETAIL E 20 11 K K1 0.25 (0.010) NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A DOES NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. MOLD FLASH OR GATE BURRS SHALL NOT EXCEED 0.15 (0.006) PER SIDE. 4. DIMENSION B DOES NOT INCLUDE INTERLEAD FLASH OR PROTRUSION. INTERLEAD FLASH OR PROTRUSION SHALL NOT EXCEED 0.25 (0.010) PER SIDE. 5. DIMENSION K DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.08 (0.003) TOTAL IN EXCESS OF THE K DIMENSION AT MAXIMUM MATERIAL CONDITION. 6. TERMINAL NUMBERS ARE SHOWN FOR REFERENCE ONLY. 7. DIMENSION A AND B ARE TO BE DETERMINED AT DATUM PLANE -W-. MILLIMETERS MIN MAX 6.40 6.60 4.30 4.50 --- 1.20 0.05 0.15 0.50 0.75 0.65 BSC 0.27 0.37 0.09 0.20 0.09 0.16 0.19 0.30 0.19 0.25 6.40 BSC 0_ 8_ INCHES MIN MAX 0.252 0.260 0.169 0.177 --- 0.047 0.002 0.006 0.020 0.030 0.026 BSC 0.011 0.015 0.004 0.008 0.004 0.006 0.007 0.012 0.007 0.010 0.252 BSC 0_ 8_ -W- DIM A B C D F G H J J1 K K1 L M NCN6000/D |
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